On chip embedded MRAM (magnetic random access memory) with non-volatility can enable energy and computational efficiency with memory density exceeding high density SRAM (static random access memory). However, leading STT-MRAM (Spin-Transfer Torque Magnetic Random Access Memory) integrated with advanced CMOS (e.g., 14 nm and smaller CMOS process technology nodes) suffer from high voltage and high current-density problems during the programming (i.e., writing operation) of a bit-cell.
For example, STT-MRAM integrated with advanced CMOS process technology exhibit insufficient drive current which is caused by intrinsic high resistance of the MRAM device during a write operation from anti-parallel to parallel state. STT-MRAM integrated with advanced CMOS process technology also exhibits high write error rates and/or low speed switching (e.g., exceeding 20 ns) in MTJ based MRAM due to the insufficient drive current. STT-MRAM integrated with advanced CMOS process technology also exhibits reliability issues due to overdriving of bits near the write driving circuitry. These and other problems are expected to grow as CMOS process scales to lower metal-0 (M0) pitches.